Location: Mountain View, CA (100% Onsite – Mon to Fri)
Duration: 12+ Months
Must-Have Skills
Strong understanding of FPGA design principles & architectures
Proficiency in SystemVerilog & UVM verification methodology
Hands-on experience in FPGA verification
Good to Have
Experience with scripting languages (Python, Perl)
Key Responsibilities
Work on FPGA design verification using industry-standard tools (QuestaSim, Synopsys VCS)
Perform code & functional coverage analysis
Debug and solve complex verification issues
Collaborate with cross-functional engineering teams
Requirements
Bachelor’s or Master’s in Electrical/Computer Engineering (or related field)
Experience in FPGA verification
Knowledge of VHDL/Verilog is a plus
Onsite Requirement: 5 Days/Week